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Seminar: Dr. Phillip Baraona and Dr. Poul Williams

"Equivalence Checking at Synopsys"

Date/Time: 

Wednesday, November 7, 2018 - 4:00pm

Presenter: 

Dr. Phillip Baraona and Dr. Poul Williams, Synopsys, INC

Location: 

Engineering Lab II Room 119

Details: 

ABSTRACT: The formality equivalence checking tool by Synopsys, INC. is one of the leading formal verification tools. It is used by companies around the world to verify their latest circuits. Most of the electronics you own probably contain chips that have been verified by Formality. In this presentation, we will outline the approach used to formally verify large, industrial designs, and we will describe some of the challenges we face.

BIO: Dr. Phillip Baraona is a senior R&D manager in the Formal Verification group at Synopsys. He has been working in the Formal Verification group for more than 20 years and has led a team of developers focused on datapath verification for the past 12 years. Phil has earned a PhD in Computer Engineering from the University of Cincinnati. Outside of work, he enjoys traveling and spending time in the woods hiking and cross country skiing.

BIO: Dr. Poul Williams is a senior staff R&D engineer in the Formal Verification group at Synopsys, INC. He has 18 years of experience developing formal verification tools, where his contributions include datapath verification and verification of ECOs. Dr. Williams got his PhD from the Technical University of Denmark. When not working, he enjoys traveling, taking photos, and writing iPhone apps.